// SPDX-License-Identifier: GPL-2.0
/*
 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 * Chanwoo Choi <cw00.choi@samsung.com>
 */

&soc {
	bus_g2d_400: bus0 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_G2D_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_g2d_400_opp_table>;
		status = "disabled";
	};

	bus_g2d_266: bus1 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_G2D_266>;
		clock-names = "bus";
		operating-points-v2 = <&bus_g2d_266_opp_table>;
		status = "disabled";
	};

	bus_gscl: bus2 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_GSCL_333>;
		clock-names = "bus";
		operating-points-v2 = <&bus_gscl_opp_table>;
		status = "disabled";
	};

	bus_hevc: bus3 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_HEVC_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_hevc_opp_table>;
		status = "disabled";
	};

	bus_jpeg: bus4 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
		clock-names = "bus";
		operating-points-v2 = <&bus_g2d_400_opp_table>;
		status = "disabled";
	};

	bus_mfc: bus5 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_MFC_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_g2d_400_opp_table>;
		status = "disabled";
	};

	bus_mscl: bus6 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_MSCL_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_g2d_400_opp_table>;
		status = "disabled";
	};

	bus_noc0: bus7 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_BUS0_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_hevc_opp_table>;
		status = "disabled";
	};

	bus_noc1: bus8 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_top CLK_ACLK_BUS1_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_hevc_opp_table>;
		status = "disabled";
	};

	bus_noc2: bus9 {
		compatible = "samsung,exynos-bus";
		clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
		clock-names = "bus";
		operating-points-v2 = <&bus_noc2_opp_table>;
		status = "disabled";
	};

	bus_g2d_400_opp_table: opp_table2 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <1075000>;
		};
		opp-267000000 {
			opp-hz = /bits/ 64 <267000000>;
			opp-microvolt = <1000000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			opp-microvolt = <975000>;
		};
		opp-160000000 {
			opp-hz = /bits/ 64 <160000000>;
			opp-microvolt = <962500>;
		};
		opp-134000000 {
			opp-hz = /bits/ 64 <134000000>;
			opp-microvolt = <950000>;
		};
		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-microvolt = <937500>;
		};
	};

	bus_g2d_266_opp_table: opp_table3 {
		compatible = "operating-points-v2";

		opp-267000000 {
			opp-hz = /bits/ 64 <267000000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
		opp-160000000 {
			opp-hz = /bits/ 64 <160000000>;
		};
		opp-134000000 {
			opp-hz = /bits/ 64 <134000000>;
		};
		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};
	};

	bus_gscl_opp_table: opp_table4 {
		compatible = "operating-points-v2";

		opp-333000000 {
			opp-hz = /bits/ 64 <333000000>;
		};
		opp-222000000 {
			opp-hz = /bits/ 64 <222000000>;
		};
		opp-166500000 {
			opp-hz = /bits/ 64 <166500000>;
		};
	};

	bus_hevc_opp_table: opp_table5 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp-267000000 {
			opp-hz = /bits/ 64 <267000000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
		opp-160000000 {
			opp-hz = /bits/ 64 <160000000>;
		};
		opp-134000000 {
			opp-hz = /bits/ 64 <134000000>;
		};
		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};
	};

	bus_noc2_opp_table: opp_table6 {
		compatible = "operating-points-v2";

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
		opp-134000000 {
			opp-hz = /bits/ 64 <134000000>;
		};
		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
		};
	};
};
